The present invention relates, in general, to cell-based integrated circuits such as gate arrays, and in particular, to an improved power and signal routing architecture and technique to achieve high density cell design for gate arrays.
Gate array technology, also known as standard cell design, has been developed as a method of quickly designing integrated circuits. Gate array technology is characterized by patterns of regularly placed transistors. The transistors are arranged in patterns known as basic cells. Basic cells are the smallest building block of the technology and are configured for dense placement and efficient signal routing. Typically, the basic cells are placed on the integrated circuit in an array pattern with rows and columns.
Basic cells are combined into predesigned circuit units known as "macro cells." Macro cells are commonly used elements such as NAND gates, NOR gates, and flip-flops. A designer selects desired elements from a library of macro cells and places them in a design. The macro cells may be interconnected in a variety of ways to perform desired functions. By being able to select macro cells from a library and place them into a design, a designer can quickly design complex functions without having to worry about the details of each individual transistor. Typically, a library of macro cells are designed from basic cells for a certain technology, and their design characteristics do not change from one design to the next.
Because a designer will use many macro cells in a particular design, it is important that the macro cells be designed as efficiently as possible. Otherwise, the inefficiencies will be multiplied, since they are replicated with every instance of the macro cell in the design.
As described above, the macro cells are made up of interconnected basic cells. Local interconnections are used to interconnect the basic cells to form macro cells. Global interconnections are used to route signal from macro cells to other macro cells, input/output terminals, and power supply sources. Clock signals, reset signals, power signals, and test signals are examples of signals that may be routed by global interconnections. It is important that the basic cells be designed such that local and global interconnections can be made efficiently.
One concern of a gate array designer is routing VDD and GROUND power supply traces to the transistors of the basic cells efficiently. FIG. 1 shows a prior art design taught, for example, in U.S. Pat. Nos. 5,072,285, 4,682,201, 4,884,118, 4,783,692, and others, to route power supply traces to basic cells.
FIG. 1 shows a portion of one row of a gate array design with two basic cells 101. Each basic cell 101 comprises a p-type diffusion region 105 and an n-type diffusion region 107. Two gate regions 113 extend across p-type diffusion region 105 forming a pair of PMOS transistors and two gate regions 115 extend across n-type diffusion region 107, forming a pair of NMOS transistors.
Several basic cells 101 are arranged in rows and columns on a substrate forming an array of basic cells 101. Power supply trace 130 extends across rows of basic cells 101 in the metal one (M1) layer above p-type diffusion region 105. Typically, power supply trace 130 is coupled to a VDD power supply source (not shown). Similarly, power supply trace 132 is formed on the M1 layer above n-type diffusion region 107, and is typically coupled to a GROUND (VSS) power supply source (not shown). Power supply traces 130 and 132 extend across rows of the array.
Most commonly, power supply traces 130 and 132 are connected to diffusion region 105 and 107 at a common node between the two transistors by contacts 140 and 142. An advantage of this layout is that a direct connection can be made between power supply traces 130 and 132 and diffusion regions 105 and 107, without additional metal routing.
Traditionally, as shown in the basic cell of FIG. 1, the M1 layer has been used to route power supply traces and other global interconnections in the direction parallel the rows (horizontal). Second layer metal (M2) has been used for global interconnections in the direction parallel the columns (vertical), and third layer metal (M3) for routing global interconnections in the direction parallel the rows (horizontal).
A disadvantage of this architectural layout is that power supply traces 130 and 132 block vertical traces on the M1 layer. This restricts the number of local interconnections that can be made on the M1 layer, thus requiring an increased use of the M2 layer to cross over power supply traces 130 and 132. For example, in FIG. 1, local interconnection 140 is located on the M2 layer in order to cross over power supply traces 130 and 132. Having local interconnections on the M2 layer causes significant blockage for M2 layer global routing, and hence lower gate density.
It is desirable to provide a more efficient routing scheme that reduces the blockage of global signal routing.